篇一：AT89S51介绍 中英文
As we all know,Single-chip is an integrated on a singlechip a complete computer system. Even
though it is very small, but it has a need to complete the majority of computer components:
CPU,memory, internal and external bus system, most will have the Core. At the sametime, such as
integrated communication interfaces, timers, real-time clock andother peripheral equipment.
Today, the most powerful single-chip microcomputersystem can even voice, image, networking,
input and output complex systemintegration on a single chip. At the begain,Single-chip also
known as single-chip MCU(Microcontroller), because it was first used in the field of
industrialcontrol. Only by the single-chip CPU chip developed from the dedicatedprocessor. Early
single-chip 8-bit or all of the four.One of the most successful is INTEL's 8031, because the
performance of a simpleand reliable access to a lot of good praise. Since then in 8031 to develop
asingle-chip microcomputer system MCS51 series. Based on single-chipmicrocomputer system of
the system is still widely used until now. As the fieldof industrial control requirements increase in
the beginning of a 16-bitsingle-chip, but not ideal because the price has not been very widely
used.After the 90's with the big consumer electronics product development,single-chip technology
is a huge improvement. INTEL i960 Series with subsequentARM in particular, a broad range of
applications, quickly replaced by 32-bitsingle-chip 16-bit single-chip high-end status, and enter
the mainstreammarket. Traditional 8-bit single-chip performance has been the rapid increasein
processing power compared to the 80's to raise a few hundred times. Atpresent, the high-end
32-bit single-chip frequency over 300MHz, the performanceof the mid-90's close on the heels of a
special processor, while the ordinaryprice of the model dropped to one U.S. dollars, the most
high-end models, only10 U.S. dollars. In today's area of Single-chip,89s51 have been "the most
outstangding person" ,which rely on their own excellent capability and the latest technology, won
more and more customers.Now,let's introduce this kind of Single-chip.
AT89S51（8-bit Micro controller with 4K Bytes Flash）
The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytes
of In-System Programmable Flash memory. The device is manufactured using Atmel's
high-density nonvolatile memory technology and is compatible with the industry-standard 80C51
instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed
in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit
CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful
microcontroller which provides a highly-flexible and cost-effective solution to many embedded
control applications.
Features：
.Compatible with MCS.-51 Products
4K Bytes of In-System Programmable (ISP) Flash Memory
一Endurance: 1000 Write/Erase Cycles
4.0V to 5.5V Operating Range
Fully Static Operation: 0 Hz to 33 MHz
Three-level Program Memory Lock
128 x 8-bit Internal RAM
32 Programmable I/O Lines
Two 16-bit Timer/Counters
Six Interrupt Sources
Full Duplex UART Serial Channel
Low-power Idle and Power-down Modes
Interrupt Recovery from Power-down Mode
Watchdog Timer
Dual Data Pointer
Power-off Flag
Fast Programming Time
Flexible ISP Programming (Byte and Page Mode)
Green (Pb/Halide-free) Packaging Option
The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32
I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two一level
interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition,
the AT89S51 is designed with static logic for operation down to zero frequency and supports two
software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM,
timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode
saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next
external interrupt or hardware reset.
VCC：
Supply voltage (all packages except 42-PDIP).
GND：
Ground (all packages except 42一PDIP; for 42-PDIP GND connects only the logic core and the
embedded program memory).
VDD：
Supply voltage for the 42-PDIP which connects only the logic core and the embedded program
memory.
PWRVDD：
Supply voltage for the 42-PDIP which connects only the I/O Pad Drivers. The application board
MUST connect both VDD and PWRVDD to the board supply voltage.
PWRGND：
Ground for the 42一PDIP which connects only the I/O Pad Drivers. PWRGND and GND are
weakly connected through the common silicon substrate, but not through any metal link. The
application board MUST connect both GND and PWRGND to the board ground.
Port 0：
Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL
inputs. When 1s are written to port 0 pins, the pins can be used as high一impedance inputs.
Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to
external program and data memory. In this mode, PO has internal pull-ups.
Port 0 also receives the code bytes during Flash programming and outputs the code bytes during
program verification. External pull-ups are required during program verification.
Port 1：
Port 1 is an 8一bit bi-directional I/O port with internal pull一ups. The Port 1 output buffers can
sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the
internal pull一ups and can be used as inputs. As inputs, Port 1 pins that are externally being
pulled low will source current (lip) because of the internal pull一ups.
Port 2：
Port 2 is an 8一bit bi-directional I/O port with internal pull一ups. The Port 2 output buffers can
sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the
internal pull一ups and can be used as inputs. As inputs, Port 2 pins that are externally being
pulled low will source current (lip) because of the internal pull一ups.
Port 2 emits the high-order address byte during fetches from external program memory and during
accesses to external data memory that use 16-bit addresses (). In this application,
Port 2 uses strong internal pull一ups when emitting 1s. During accesses to external data memory
that use 8-bit addresses (), Port 2 emits the contents of the P2 Special Function
Register.
Port 2 also receives the high-order address bits and some control signals during Flash
programming and verification.
Port 3：
Port 3 is an 8一bit bi-directional I/O port with internal pull一ups. The Port 3 output buffers can
sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the
internal pull一ups and can be used as inputs. As inputs, Port 3 pins that are externally being
pulled low will source current (lip) because of the pull-ups.
Port 3 receives some control signals for Flash programming and verification.
Port 3 also serves the functions of various special features of the AT89S51，as shown in the
following table.
RST：
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the
device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO
bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit
DISRTO, the RESET HIGH out feature is enabled.
ALE/PROG：
Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG) during Flash
programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator
frequency and may beused for external timing or clocking purposes. Note, however, that one ALE
pulse is skipped during each access to external data memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set,
ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled
high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
PSEN：
Program Store Enable (PSEN) is the read strobe to external program memory.
When the AT89S51 is executing code from external program memory, PSEN is activated twice
each machine cycle, except that two PSEN activations are skipped during each access to external
data memory.
EA/VPP：
External Access Enable. EA must be strapped to GND in order to enable the device to fetch code
from external program memory locations starting at OOOOH up to FFFFH. Note, however, that if
lock bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to Vcc for internal program executions.
This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.
XTAL1：
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2：
Output from the inverting oscillator amplifier
Special Function Registers：
Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented
on the chip. Read accesses to these addresses will in general return random data, and write
accesses will have an indeterminate effect.
User software should not write 1 s to these unlisted locations, since they may be used in future
products to invoke new features. In that case, the reset or inactive values of the new bits will
always be 0.
Interrupt Registers:
The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the
five interrupt sources in the IP register.
Dual Data Pointer Registers:
To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer
Registers are provided: DPO at SFR address locations 82H-83H and DP1 at 84H-85H.Bit DPS=0
in SFR AUXR1 selects DPO and DPS=1 selects DP1. The user should ALWAYS initialize the
DPS bit to the appropriate value before accessing the respective Data Pointer Register.
Power Off Flag:
The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to "1”during
power up. It can be set and rest under software control and is not affected by reset.
Memory Organization：
MCS-51 devices have a separate address space for Program and Data Memory. Up to 64Kbytes each of external Program and Data Memory can be addressed.
Program Memory：
If the EA pin is connected to GND, all program fetches are directed to external memory. On the
AT89S51，if EA is connected to Vcc, program fetches to addresses OOOOH through FFFH are
directed to internal memory and fetches to addresses 1000H through FFFFH are directed to
external memory.
Data Memory：
The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct and
indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes
of data RAM are available as stack space.
Watchdog Timer (One-time Enabled with Reset-out)：
The WDT is intended as a recovery method in situations where the CPU may be subjected to
software upsets. The WDT consists of a 14一bit counter and the Watchdog Timer Reset
(WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user
must write 01 EH and OE1 H in sequence to the WDTRST register (SFR location OA6H). When
the WDT is enabled, it will increment every machine cycle while the oscillator is running. The
WDT timeout period is dependent on the external clock frequency. There is no way to disable the
WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows,
it will drive an output RESET HIGH pulse at the RST pin.
Timer 0 and 1：
Timer 0 and Timer 1 is a 16-bit Timer/Counter
我们都知道，单片机是指一个集成在一块芯片上的完整计算机系统。尽管它很小，但是它具有一个完整计算机所需要的大部分部件：CPU、内存、内部和外部总线系统。到了今天，最强大的单片机系统甚至可以将声音、图像、网络、复杂的输入输出系统集成在一块芯片上。开始时，单片机也曾被称为微控制器（Microcontroller），是因为它最早被用在工业控制领域。单片机由芯片内仅有CPU的专用处理器发展而来。早期的单片机都是8位或4位的。其中最成功的是INTEL的8031，因为简单可靠而性能不错获得了很大的好评。此后在8031上发展出了MCS51系列单片机系统。基于这一系统的单片机系统直到现在还在广泛使用。随着工业控制领域要求的提高，开始出现了16位单片机，但因为性价比不理想并未得到很广泛的应用。90年代后随着消费电子产品大发展，单片机技术得到了巨大的提高。随着INTEL i960系列特别是后来的ARM系列的广泛应用，32位单片机迅速取代16位单片机的高端地位，并且进入主流市场。而传统的8位单片机的性能也得到了飞速提高，处理能力比起80年代提高了数百倍。目前，高端的32位单片机主频已经超过300MHz，性能直追90年代中期的专用处理器，而普通的型号出厂价格跌落至1美元，最高端的型号也只有10美元。在如今的单片机领域，89S51已经成为了佼佼者，其依靠自身的优异性能和最新技术，赢得了越来越多的用户青睐。现在，我们就来介绍此种单片机。
AT89S51 (8位微控制单片机，片内含4K bytes可系统编程的存储器)
AT89S51是美国ATMEL公司生产的低功耗，高性能CMOS 8位单片机，片内含4k bytes的可系统编程的Flash只读程序存储器，器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准8051指令系统及引脚。它集Flash程序存储器既可在线编程（ISP)也可用传统方法进行编程及通用8位微处理器于单片芯片中，ATMEL公司的功能强大，低价位AT89S51单片机可为您提供许多高性价比的应用场介，可灵活应用于各种控制领域。 主要性能参数：
·与MCS-51 产品指令系统完全兼:容
·4k字节在线系统编程(ISP) Flash闪速存储器
·1000次擦写周期
·4. 0---5. 5V的工作电压范围
·全静态工作模式：0Hz---33MHz
·三级程序加密锁
·128×8字节内部RAM
·32个可编程I/O口线
·2个16位定时/计数器
·6个中断源
·全双工串行UART通道
·低功耗空闲和掉电模式
·中断可从空闲模式唤醒系统
·看门狗(WDT)及双数据指针
·掉电标识和快速编程特性
·灵活的在线系统编程(ISP一字节或页写模式)
功能特性概述：
篇二：AT89S51中英文说明
AT89S51 (8位微控制单片机，片内含4K bytes可系统编程的存储器)
AT89S51是美国ATMEL公司生产的低功耗，高性能CMOS 8位单片机，片内含4k bytes的可系统编程的Flash只读程序存储器，器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准8051指令系统及引脚。它集Flash程序存储器既可在线编程（ISP)也可用传统方法进行编程及通用8位微处理器于单片芯片中，ATMEL公司的功能强大，低价位AT89S51单片机可为您提供许多高性价比的应用场介，可灵活应用于各种控制领域。 主要性能参数：
·与MCS-51 产品指令系统完全兼:容
·4k字节在线系统编程(ISP) Flash闪速存储器
·1000次擦写周期
·4. 0---5. 5V的工作电压范围
·全静态工作模式：0Hz---33MHz
·三级程序加密锁
·128×8字节内部RAM
·32个可编程I/O口线
·2个16位定时/计数器
·6个中断源
·全双工串行UART通道
·低功耗空闲和掉电模式
·中断可从空闲模式唤醒系统
·看门狗(WDT)及双数据指针
·掉电标识和快速编程特性
·灵活的在线系统编程(ISP一字节或页写模式)
功能特性概述：
AT89S51提供以下标准功能：4k字节Flash闪速存储器，128字节内部RAM， 32个I/O口线，看门狗（WDT），两个数据指针，两个16位定时/计数器，一个5向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。同时，AT89S51可降至0Hz的静态逻辑操作，并支持两种软件可选的节电工作模式。空闲方式停止CPU的工作，但允许RAM，定时/计数器，串行通信口及中断系统继续工作。掉电方式保存RAM中的内容，但振荡器停止工作并禁止其它所有部件工作直到下一个硬件复位。
引脚功能说明：
·Vcc： 电源电压
·GND：地
·P0口：P0口是一组8位漏极开路型双向I/O口，也即地址/数据总线复用口。作为输出口用时，每位能驱动8个TTL逻辑门电路，对端口写?1?可作为高阻抗输入端用。
在访问外部数据存储器或程序存储器时，这组口线分时转换地址(低8位)和数据总线复用，在访问期间激活内部上拉电阻。
在Flash编程时，P0 口接收指令字节，而在程序校验时，输出指令字节，校验时，要求外接上拉电阻。
·P1口：P1是一个带内部上拉电阻的8位双向I/O口，P1的输出缓冲级可驱动(吸收或输出电流)4个TTL逻辑门电路。对端口写?1?，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作输入口使用时，囚为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流(In)。
Flash编程和程序校验期间 P 1接收低8位地址。
·P2口：P2是一个带有内部上拉电阻的8位双向I/O口，P2的输出缓冲级可驱动(吸收或输出电流)4个TTL逻辑门电路。对端口写?1?，通过内部的上拉电阻把端口拉到高电平，此时可作输入口，作输入口使用时，囚为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流(In)。
在访问外部程序存储器或16位地址的外部数据存储器(例如执行MOVX @DPTR指令)时，P2口送出高 8位地址数据。在访问8位地址的外部数据存储器(如执行MOVX @Ri指令)时，P2口线卜的内容(也即特殊功能寄存器（SFR)区中P2寄存器的内容)，在整个访问期间不改变。 Flash编程或校验时，P2亦接收高位地址和其它控制信号。
·P3口：P3口是一组带有内部上拉电阻的8位双向I/O口。P3口输出缓冲级可驱动(吸收或输出电流)4个TTL逻辑门电路。对P3 口写入“1”时，它们被内部上拉电阻拉高并可作为输入端口。作输入端时，被外部拉低的P3 口将用上拉电阻输出电流（In）。
P3口除了作为一般的I/O口线外，更重要的用途是它的第二功能。
P3 口还接收一些用于Flash闪速存储器编程和程序校验的控制信号。
·RST：复位输入。当振荡器工作时，RST引脚出现两个机器周期以上高电平将使单片机复位。WDT溢出将使该引脚输出高电平，设置SFR AUXR 的DISRTO位（地址8EH）可打开或关闭该功能。DISRTO位缺省为RESET输出高电平打开状态。
·ALE/PROG：当访问外部程序存储器或数据存储器时，ALE(地址锁存允许)输出脉冲用于锁存地址的低8位字节。即使不访问外部存储器，ALE仍以时钟振荡频率的1/6输出固定的正脉冲信号，囚此它可对外输出时钟或用于定时目的。要注意的是：每当访问外部数据存储器时将跳过一个ALE脉冲。
对Flash存储器编程期间，该引脚还用于输入编程脉冲（PROG）。
如有必要，可通过对特殊功能寄存器（SFR)区中的8EH单元的D0位置位，可禁正ALE操作。该位置位后，只有一条MOVX和MOVC指令ALE才会被激活。此外，该引脚会被微弱拉高，单片机执行外部程序时，应设置ALE无效。
·PSEN：程序储存允许(PSEN)输出是外部程序存储器的读选通信号，当AT89S51由外部程序存储器取指令(或数据)时，每个机器周期两次PSEN有效，即输出两个脉冲。当访问外部数据存储器，没有两次有效的PSEN信号。
·EA/VPP：外部访问允许。欲使CPU仅访问外部程序存储器(地址为0000H-FFFFH), EA端必须保持低电平(接地)。需注意的是：如果加密位LB1被编程，复位时内部会锁存EA端状态。 如EA端为高电平(接Vcc端)，CPU则执行内部程序存储器中的指令。
Flash存储器编程时，该引脚加上+12 V的编程电压Vpp。
·XTAL 1：振荡器反相放大器及内部时钟发生器的输入端。
·XTAL2：振荡器反相放大器的输出端。
·特殊功能寄存器：
特殊功能寄存器的于片内的空间分布的这些地址并没有全部占用，没有占用的地址亦不可使用，读这些地址将得到一个随意的数值。而写这些地址单元将不能得到预期的结果。 ·中断寄存器：
各中断允许控制位于IE寄存器，5个中断源的中断优先级控制位于IP寄存器。
·双时钟指针寄存器：
为更方便地访问内部和外部数据存储器，提供了两个16位数据指针寄存器：DP0位于SFR(特殊功能寄存器)区块中的地址82H, 83H和DP1位于地址84H, 85H，当SFR中的位DPS=0选择DP0，而DPS=1则选择DP1。用户应在访问相应的数据指针寄存器前初始化DPS位。
·电源空闲标志：
电源空闲标志（POF）在特殊功能寄存器SFR中PCON的第4位(PCON.4}，电源打开时POF置?1?，它可由软件设置睡眠状态并不为复位所影响。
·程序存储器：
如果EA引脚接地(GND)，全部程序均执行外部存储器。
在AT89S51,假如EA接至Vcc(电源+)，程序首先执行地址从0000H-OFFFH （4KB）内部程序存储器，而执行地址为1000H-FFFFH (60KB)的外部程序存储器。
·数据存储器：
AT89S51的具有128字节的内部RAM，这128字节可利用直接或间接寻址方式访问，堆栈操作可利用间接寻址方式进行，128字节均可设置为堆栈区空间。
·看门狗定时器(WDT)：
WDT是为了解决CPU程序运行时可能进入混乱或死循环而设置，它由一个14bit计数器和看门狗复位SFR (WDTRST)构成。外部复位时，WDT默认为关闭状态，要打开WDT，用户必须按顺序将01EH和0E1H写到WDTRST寄存器（SFR地址为OA6H},当启动了WDT，它会随晶体振荡器在每个机器周期计数，除硬件复位或WDT溢出复位外没有其它方法关闭WDT，当WDT溢出，将使RSF引脚输出高电平的复位脉冲。
·定时器0和定时器1：
定时器0和1都是一个16位定时/计数器。
AT89S51（8-bit Micro controller with 4K Bytes Flash）
The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytes
of In-System Programmable Flash memory. The device is manufactured using Atmel's high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.
Features：
.Compatible with MCS.-51 Products
4K Bytes of In-System Programmable (ISP) Flash Memory
一Endurance: 1000 Write/Erase Cycles
4.0V to 5.5V Operating Range
Fully Static Operation: 0 Hz to 33 MHz
Three-level Program Memory Lock
128 x 8-bit Internal RAM
32 Programmable I/O Lines
Two 16-bit Timer/Counters
Six Interrupt Sources
Full Duplex UART Serial Channel
Low-power Idle and Power-down Modes
Interrupt Recovery from Power-down Mode
Watchdog Timer
Dual Data Pointer
Power-off Flag
Fast Programming Time
Flexible ISP Programming (Byte and Page Mode)
Green (Pb/Halide-free) Packaging Option
The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two一level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.
VCC：
Supply voltage (all packages except 42-PDIP).
GND：
Ground (all packages except 42一PDIP; for 42-PDIP GND connects only the logic core and the embedded program memory).
VDD：
Supply voltage for the 42-PDIP which connects only the logic core and the embedded program memory.
PWRVDD：
Supply voltage for the 42-PDIP which connects only the I/O Pad Drivers. The application board MUST connect both VDD and PWRVDD to the board supply voltage.
PWRGND：
Ground for the 42一PDIP which connects only the I/O Pad Drivers. PWRGND and GND are weakly connected through the common silicon substrate, but not through any metal link. The application board MUST connect both GND and PWRGND to the board ground.
Port 0：
Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high一impedance inputs.
Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, PO has internal pull-ups.
Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.
Port 1：
Port 1 is an 8一bit bi-directional I/O port with internal pull一ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull一ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (lip) because of the internal pull一ups.
Port 2：
Port 2 is an 8一bit bi-directional I/O port with internal pull一ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull一ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (lip) because of the internal pull一ups.
Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (). In this application, Port 2 uses strong internal pull一ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (), Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
Port 3：
Port 3 is an 8一bit bi-directional I/O port with internal pull一ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull一ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (lip) because of the pull-ups.
Port 3 receives some control signals for Flash programming and verification.
Port 3 also serves the functions of various special features of the AT89S51，as shown in the following table.
RST：
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.
ALE/PROG：
Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may beused for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. PSEN：
Program Store Enable (PSEN) is the read strobe to external program memory.
When the AT89S51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.
EA/VPP：
External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at OOOOH up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to Vcc for internal program executions.
This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming. XTAL1：
Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2：
Output from the inverting oscillator amplifier
篇三：AT89S51概述 英文资料 The Description of AT89S51
AT89S51概述
1 一般概述
该AT89S51是一个低功耗，高性能CMOS 8位微控制器,可在4K字节的系统内编程的闪存存储器。该设备是采用Atmel的高密度非易失性存储器技术和符合工业标准的80C51指令集和引脚。芯片上的Flash程序存储器可重新编程的系统或常规非易失性内存编程 。通过结合通用8位中央处理器的系统内可编程闪存的单芯片， AT89S51是一个功能强大的微控制器提供了高度灵活的和具有成本效益的解决办法，可在许多嵌入式控制中应用。
在AT89S51提供以下标准功能： 4K字节的Flash闪存 ， 128字节的RAM ， 32个 I / O线，看门狗定时器，两个数据指针，两个16位定时器/计数器， 5向量两级中断结构，全双工串行端口，片上振荡器和时钟电路。此外， AT89S51设计的静态逻辑操作到零频率和支持两种软件可选节电模式。
空闲模式停止的CPU ，同时允许的RAM ，定时器/计数器，串行接口和中断系统继续运作。在掉电模式保存RAM内容，可停止振荡器，停用所有其他芯片的功能，直到下一个外部中断或硬件复位。
2 端口
端口0是一个8位漏极开路双向I / O端口。作为一个输出端口，每个引脚可汇8的TTL输入。当1写入端口0引脚，该引脚可作为高阻抗输入。端口0也可以配置为复低阶地址/数据总线，在访问外部程序和数据存储器。在这种模式下， P0了内部无上拉。端口还收到0字节的代码在Flash编程和产出代码波特率的核查。外部上拉需要在使用。
端口1是一个8位双向I / O端口内部上拉。端口1输出缓冲器可以驱动四个TTL。当1写入端口1引脚，他们的退出高足态上拉，可作为输入。作为输入，端口1引脚的外部被拉低将电源电流（ IIL ）由于内部上拉。端口1还收到低字节为了解决在Flash编程和核查。
端口2是一个8位双向I / O端口内部上拉。端口2输出缓冲器可以驱动四的TTL输入。当1写入端口2，他们的退出高阻态上拉，可作为输入。作为输入，端口2引脚的外部被拉低将电源电流（ IIL ）由于内部上拉。端口2排放高阶地址字节在获取外部程序存储器和杜尔法访问外部数据存储器，使用16位地址（ MOVX @ DPTR ） 。在此应用程序，端口2使用强大的内部上拉时，发射谱。在访问外部数据存储器，使用8位地址（ MOVX @里） ，端口2发出的内容， P2的特殊功能寄存器。端口2还收到高阶地址位和一些控制信号在闪存程序明和核查。
端口3是8位双向I / O端口内部上拉。端口3输出缓冲器可以驱动四个TTL输入。当1写入端口3引脚，他们的退出高阻态上拉，可作为输入。作为输入，端口3引脚的外部被拉低将电源电流（ IIL ）因为上拉。端口3获得某种程度的控制信号的Flash编程和核查。端口3兼任的职能。
3 特殊功能寄存器
图上的片上存储器区域称为特殊功能寄存器（ SFR的）。请注意，并非所有的地址都被占领，未使用的的地址可以寻址。阅读访问这些地址将一般返回随机数据，写访问将有不确定的结果。
用户软件不应该写入对这些非寻址地址。在这种情况下，重置值或无效的新的双向数据将永远是0 。中断寄存器：个人中断启用BITS是在IE注册。两个优先级可以设定为每一个中断源的优先顺序。
双数据指针寄存器：为了便于访问内部和外部数据存储器，这两家指针的16位数据指针寄存器提供： DP0地点在SFR的地址82H - 83H和DP1在84H - 85H 。位的DPS = 0中的SFR选择DP0和AUXR1的DPS = 1选择DP1 。
用户应始终初始化的DPS位到适当的值之前，各自的数据存取指针寄存器。
断电检举：电源（光纤）位于位4 （ PCON.4 ）在PCON SFR。它可以设置和其他软件的控制下，是不会受到影响复位。
4 存储设备
MCS - 51单片机的设备有一个单独地址空间的程序和数据存储器。高达64K字节的外部程序和数据存储器可以得到解决。
4.1 程序存储器
如果的EA引脚连接到GND ，获取所有程序都是针对外部存储器。关于AT89S51 ，如果EA连接到VCC ，计划获取地址0000H通过FFFH是针对内部存储器和存取的地址1000H通过FFFFH是针对外部存储器。
4.2 数据存储器
AT89S51实施的128字节的片上RAM 。 128字节都可以通过直接和间接寻址模式。栈操作的例子间接寻址，因此， 128字节的数据RAM可作为堆栈空间。
5 定时器
看门狗定时器（一次性启用了复位输出）的定时器是作为恢复方法的情况下的CPU可能会受到软件冷门。该定时器包括一个14位计数器和看门狗定时器复位（ WDTRST ） SFR公司。该定时器是拖欠禁用从朝重置。为了使定时器，用户必须写入01EH和0E1H依次向WDTRST寄存器（ SFR的位置0A6H ） 。当定时器启用，它会增加，而每个机器周期振荡器正在运行。该定时器超时时间依赖于外部时钟频率。没有办法禁用定时器除了通过重置（或者硬件复位或定时器溢出复位） 。当定时器过度流动，将驱动器输出复位高脉冲的复位引脚。
为了使定时器，用户必须写入01EH和0E1H顺序登记的WDTRST（ SFR的位置
0A6H ） 。当定时器被激活，用户需要的服务以书面01EH和0E1H到WDTRST以避免定
时器溢出。 14位计数器溢出时，达到16383 （ 3FFFH ） ，这将重置该设备。当定时器启用，它会增加，而每个机器周期振荡器正在运行。这意味着用户必须重置定时器至少每16383机器周期。重置定时器用户必须写入01EH和0E1H到WDTRST 。 WDTRST是一个只写寄存器。该定时器计数器无法读取或写入。当定时器溢出，它会产生一个输出复位脉冲的复位引脚。重置脉冲硬脑膜化是98xTOSC ，其中TOSC = 1/FOSC 。以最佳方式利用的定时器，应当在提供服务的部分代码，将定期予以执行规定的时间内，以防止定时器复位。
在掉电模式振荡器停止，这意味着定时器也会停止。而在省电模式，用户并不需要提供服务的定时器。方法有两种退出省电模式：由硬件复位或通过一级激活外部中断，这是启用之前，进入掉电模式。当电源式是退出硬件复位，服务定时器应该发生，因为它通常不每当AT89S51重置。朝电力中断下明显不同。中断是足够长的时间举行低的振荡器稳定。如果中断是使高，中断提供服务。为了防止从重置定时器的装置而中断引脚举行低，定时器未启动之前，中断被拉高。有人建议，定时器重置在中断服务的中断用来退出掉电模式。为了确保定时器不会溢出的少数几个国家的退出省电，最好是重置定时器刚刚进入掉电模式。在进入空闲模式，该WDIDLE位的SFR AUXR是用来确定是否该定时器继续计数如果启用。计数的定时器保持在闲置（ WDIDLE位= 0 ）作为默认的状态。为了防止定时器从重置AT89S51 ，而在空闲模式下，用户应始终成立一个计时器，将定期退出闲置，服务的定时器，并重新输入空闲模式。
与WDIDLE位启用，定时器将停止指望在空闲模式和简历伯爵离开时从闲置。
定时器0和定时器1在AT89S51操作一样定时器0和定时器1的AT89C51单片机。如需进一步信息的定时器操作，请单击文件以下链接：
/dyn/resources/prod_documents/DOC4316.PDF
6 中断
该AT89S51共有5个中断向量：两个外部中断（ INT0和INT1 ） ，两个定时器中断（定时器0和1 ） ，和串口中断。这些中断都如图10-1 。所有这些中断源可以单独启用或禁用的设置或清除有点特殊功能寄存器IE浏览器。 IE浏览器还包含一个全球禁用位，电子艺界，这将禁用所有中断一次。
请注意，表10-1表明位立场IE.6和IE.5正在得到执行。用户软件不应该写谱这些位的职位，因为它们可能被用来在今后AT89产品。定时器0和定时器1旗帜， TF0和TF1电视台，分别为S5P2周期中，定时器溢出。的价值观，然后调查的电路中的下一个周期。 7 振荡器特性
XTAL1和XTAL2是输入和输出，分别是反相放大器，可配置为使用一个片上振荡器，如图所示的11月1日。或者石英晶体或陶瓷谐振器可以使用。驱动装置由外部时钟源， XTAL2应留待无关而XTAL1驱动所示，图11月2日。没有规定的工作周期的外部时钟信
号，因为输入到内部时钟化电路是通过鸿沟通过两个触发器，但最低和最高电压高和低时间规格必须得到遵守。
8 闲置模式
在空闲模式时， CPU让自己休眠，而所有片上外设仍然很活跃。该模式是由软件设置的内容，在这一模式，片上RAM和所有特殊功能寄存器值保持不变。闲置模式可终止任何启用中断或硬件复位。
请注意，当空闲模式终止硬件复位，恢复正常的装置亲克执行从上次结束的地方，两个机器周期之前，内部复位控制算法。片上硬件阻止访问内部RAM在这一事件，但进入端口引脚不受控制。为了消除可能意外写入端口引脚空闲模式时终止复位的指令后，空闲模式不应写入端口引脚或外部存储器。
断电模式的省电模式时，振荡器停止，并指示，调用省电是最后指示执行。片上RAM和特殊功能寄存器保持其价值，直到掉电模式终止。退出掉电模式可以开始由硬件复位或通过激活一个启用外部中断（ INT0或INT1 ） 。重置重新定义了SFR但不改变片上RAM 。重置不应在激活之前，虚拟通道连接恢复其正常工作的程度，必须积极争取足够的时间使振荡器重新启动并稳定下来。
The Description of AT89S51
1 General Description
The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytes of In-System Programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the indus-try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-grammer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.
The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM con-tents but
freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.
2 Ports
Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-ing program verification. External pull-ups are required during program verification.
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 1 also receives the low-order address bytes during Flash programming and verification.
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.Port 2 emits the high-order address byte during fetches from external program memory and dur-ing accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash program-ming and verification.
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S51, as shown in the fol-lowing table.
3 Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 5-1. Note that not all of the addresses are occupied, and unoccupied addresses may not be imple-mented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
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