篇一：AT89S51单片机外文翻译
The Description of AT89S51
1 General Description
The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytes of In-System Programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.
The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset. 2 Ports
Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal
pull-ups.
Port 1 also receives the low-order address bytes during Flash programming and verification.
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S51, as shown in the following table.
3 Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 3-1.
0F8H 0F0H 0E8H 0E0H 0D8H 0D0H 0C8H 0C0H 0B8H 0B0H 0A8H 0A0H 98H
90H
88H
0FFH
0F7H
0EFH
0E7H
0DFH
0D7H
0CFH
0C7H
0BFH
0B7H
0AFH
0A7H
9FH
97H
8FH
80H
87H
Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations, since they may be
used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.
Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the five interrupt sources in the IP register.
Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.
Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and rest under software control and is not affected by reset.
4 Memory Organization
MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed. 4.1 Program Memory
CC, program fetches to addresses 0000H through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory. 4.2 Data Memory
The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space. 5 Watchdog Timer (One-time Enabled with Reset-out)
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through
篇二：AT89s51单片机外文翻译
毕业设计（论文）外文翻译
毕业设计（论文）题目：基于单片机的点阵LED显示屏系统的设计
外文题目：The Description of AT89S51
译文题目：AT89S51概述
学生姓名： 费禹翔 专 业：电气工程及其自动化0603班 指导教师： 李翠玉
The Description of AT89S51
1 General Description
The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytes of In-System Programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.
The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset. 2 Ports
Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal
pull-ups.
Port 1 also receives the low-order address bytes during Flash programming and verification.
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S51, as shown in the following table.
3 Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 3-1.
0F8H 0F0H 0E8H 0E0H 0D8H 0D0H 0C8H 0C0H 0B8H 0B0H 0A8H 0A0H 98H
90H
88H
0FFH
0F7H
0EFH
0E7H
0DFH
0D7H
0CFH
0C7H
0BFH
0B7H
0AFH
0A7H
9FH
97H
8FH
80H
87H
Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations, since they may be
used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.
Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the five interrupt sources in the IP register.
Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.
Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and rest under software control and is not affected by reset.
篇三：AT89S51单片机
AT89S51
AT89S51单片机的硬件组成
单片机内硬件组成结构如图2-1所示。
图2-1 AT89S51单片机片内结构
有如下功能部件和特性：
（1）8位微处理器（CPU）；
（2）数据存储器（128B RAM）；
（3）程序存储器（4KB Flash ROM）；
（4）4个8位可编程并行I/O口（P0口、P1口、P2口和P3口）；
（5）1个全双工的异步串行口；
（6）2个可编程的16位定时器/计数器；
（7）1个看门狗定时器；
（8）中断系统具有5个中断源、5个中断向量；
（9）特殊功能寄存器（SFR）26个；
（10）低功耗模式有空闲模式和掉电模式，且具有掉电模式下的中断恢复模式；
（11）3个程序加密锁定位。
与AT89C51相比，AT89S51有更突出的优点：
（1）增加在线可编程功能ISP（In System Program），字节和页编程，现场程序调试和修改更加方便灵活；
（2）数据指针增加到两个，方便了对片外RAM的访问过程；
（3）增加了看门狗定时器，提高了系统的抗干扰能力；
（4）增加断电标志；
（5）增加掉电状态下的中断恢复模式。
单片机内各功能部件通过片内单一总线连接而成（见图2-1），基本结构依旧是CPU 加上外围芯片的传统微机结构。
CPU对各种功能部件的控制是采用特殊功能寄存器（SFR，Special Function Register）的集中控制方式。 单片机内部件功能
1）CPU（微处理器）
8位的CPU，与通用CPU基本相同，同样包括了运算器和控制器两大部分，还有面向控制的位处理功能。
2）数据存储器（RAM）
片内为128B（52子系列为256B），片外最多可扩64KB。片内128B的RAM以高速RAM的形式集成，可加快单片机运行的速度和降低功耗。
3）程序存储器（Flash ROM）
片内集成有4KB的Flash存储器（AT89S52 则为8KB；AT89C55片内20KB），如片内容量不够，片外可外扩至64KB。
4）中断系统
具有5个中断源，2级中断优先权。
5）定时器/计数器
2个16位定时器/计数器（52子系列有3个），4种工作方式。
6）1个看门狗定时器WDT
当CPU由于干扰使程序陷入死循环或跑飞时，WDT可使程序恢复正常运行。
7）串行口
1个全双工的异步串行口，4种工作方式。可进行串行通信，扩展并行I/O口，还可与多个单片机构成多机系统。
8）P0口、P1口、P2口和P3口
4个8位并行I/O口。
9）特殊功能寄存器（SFR）
26个，对片内各功能部件管理、控制和监视。是各个功能部件的控制寄存器和状态寄存器，映射在片内RAM区80H～FFH内。
AT89S51完全兼容AT89C51，在充分保留原来软、硬件条件下，完全可以用AT89S51直接代换。 AT89S51的引脚功能
AT89S51与51系列中各种型号芯片的引脚互相兼容。目前多采用40只引脚双列直插，如图2-2所示。 引脚按其功能可分为如下3类：
1）电源及时钟引脚—VCC、VSS；XTAL1、XTAL2。
2）控制引脚—、ALE/ PROG 、/VPP、RST（RESET） EAPSEN3）I/O口引脚——P0、P1、P2、P3，为4个8位I/O口
电源及时钟引脚
1．电源引脚
1）VCC（40脚）：+5V电源。
2）VSS（20脚）：数字地。
2．时钟引脚
1）XTAL1（19脚）：片内振荡器反相放大器和时钟发生器电路输入端。用片内振荡器时，该脚接外部石英晶体和微调电容。外接时钟源时，该脚接外部时钟振荡器的信号。
2）XTAL2（18脚）：片内振荡器反相放大器的输出端。当使用片内振荡器，该脚连接外部石英晶体和微调电容。当使用外部时钟源时，本脚悬空。
3．控制引脚
1）RST (RESET，9脚)
复位信号输入，在引脚加上持续时间大于2个机器周期的高电平，可使单片机复位。正常工作，此脚电平应 ≤ 0.5V。
当看门狗定时器溢出输出时，该脚将输出长达96个时钟振荡周期的高电平。
2）/VPP (Enable Address/Voltage Pulse of Programing，31脚) EAEA引脚第一功能：外部程序存储器访问允许控制端。
=1：在PC值不超出0FFFH（即不超出片内4KB Flash存储器的地址范围）时，单片机读片内程序存储器（4KB）中的程序，但PC值超出0FFFH （即超出片内4KB Flash地址范围）时，将自动转向读取片外60KB（1000H-FFFFH）程序存储器空间中的程序。 EA=0：只读取外部的程序存储器中的内容，读取的地址范围为0000H～FFFFH，片内的4KB Flash 程序存储器不起作用。
VPP：引脚第二功能，对片内Flash编程，接编程电压。
3）ALE/ PROGAddress Latch Enable/PROGramming，30脚）
ALE为CPU访问外部程序存储器或外部数据存储器提供地址锁存信号，将低8位地址锁存在片外的地址锁存器中。此外，单片机正常运行时，ALE端一直有正脉冲信号输出，此频率为时钟振荡器频率fosc的1/6。可用作外部定时或触发信号。
注意，每当AT89S51访问外部RAM时（执行MOVX类指令），要丢失一个ALE脉冲。
如需要，可将特殊功能寄存器AUXR（地址为8EH，将在后面介绍）的第0位（ALE禁止位）置1，来禁止ALE操作，但执行访问外部程序存储器或外部数据存储器指令“MOVC”或“MOVX”时，ALE仍然有效。即ALE禁止位不影响对外部存储器的访问。
：引脚第二功能，对片内 Flash编程，为编程脉冲输入脚。 PROG
图2-2 AT89S51双列直插封装方式的引脚 PSEN4） （Program Strobe ENable，29脚）
片外程序存储器读选通信号，低电平有效。
并行I/O口引脚
1）P0口：8位，漏极开路的双向I/O口
当外扩存储器及I/O接口芯片时，P0口作为低8位地址总线及数据总线的分时复用端口。
P0口也可用作通用的I/O口，需加上拉电阻，这时为准双向口。作为通用I/O输入，应先向端口写入1。可驱动8个LS型TTL负载。
2）P1口：8位，准双向I/O口，具有内部上拉电阻。
准双向I/O口，作为通用I/O输入时，应先向端口锁存器写1。
P1口可驱动4个LS型TTL负载。
P1.5/MOSI、P1.6/MISO和P1.7/SCK
可用于对片内Flash存储器串行编程和校验，它们分别是串行数据输入、输出和移位脉冲引脚。
3）P2口：8位，准双向I/O口，具有内部上拉电阻。
当AT89S51扩展外部存储器及I/O口时，P2口作为高8位地址总线用，输出高8位地址。
P2口也可作为普通的I/O口使用。当作为通用I/O输入时，
应先向端口输出锁存器写1。P2口可驱动4个LS型TTL负载。
4）P3口：8位，准双向I/O口，具有内部上拉电阻。
可作为通用的I/O口使用。作为通用I/O输入，应先向端口输出锁存器写入1。可驱动4个LS型TTL负载。 P3口还可提供第二功能。第二功能定义见表2-1，应熟记。
表2-1P3口的第二功能定义
综上所述，P0口可作为总线口，为双向口。作为通用的I/O口使用时，为准双向口，这时需加上拉电阻。P1口、P2口、P3口均为准双向口。
注意：准双向口与双向口的差别。准双向口仅有两个状态。而P0口作为总线使用，口线内无上拉电阻，处于高阻“悬浮”态。故P0口为双向三态I/O口。
为什么P0口要有高阻“悬浮”态？
准双向I/O口则无高阻的“悬浮”状态。
另外，准双向口作通用I/O的输入口使用时，一定要向该口先写入“1”。以上的准双向口与双向口的差别，读者在阅读2.5节后，将会有深刻的理解。
至此，40个引脚已介绍完，应熟记每一引脚功能对应用系统硬件电路设计十分重要。
AT89S51的CPU(p41)
由图2-1可见，CPU由运算器和控制器构成。
一、运算器
对操作数进行算术、逻辑和位操作运算。主要包括算术逻辑运算单元ALU、累加器A、位处理器、程序状态字寄存器PSW及两个暂存器等。
1．算术逻辑运算单元ALU
可对8位变量逻辑运算（与、或、异或、循环、求补和清零），还可算术运算（加、减、乘、除）
ALU还有位操作功能，对位变量进行位处理，如置“1”、清“0”、求补、测试转移及逻辑“与”、“或”等。
2．累加器A
使用最频繁的寄存器，可写为Acc。“A”与“Acc” 书写上的差别，将在第3章介绍。
作用如下：
1）ALU单元的输入数据源之一，又是ALU运算结果存放单元。
2）数据传送大多都通过累加器A，相当于数据的中转站。为解决“瓶颈堵塞”问题，AT89S51增加了一部分可以不经过累加器的传送指令。
A的进位标志Cy是特殊的，因为它同时又是位处理机的位累加器
3．程序状态字寄存器PSW
PSW（Program Status Word）位于片内特殊功能寄存器区，字节地址为D0H。
包含了程序运行状态的信息，其中4位保存当前指令执行后的状态，供程序查询和判断。格式如图2-3所示。
图2-3 PSW的格式
PSW中各个位的功能：
1）Cy（PSW.7）进位标志位
可写为C。在算术和逻辑运算时，若有进位/借位，Cy＝1；否则，Cy＝0。在位处理器中，它是位累加器。
2）Ac（PSW.6）辅助进位标志位
在BCD码运算时，用作十进位调
整。即当D3位向D4位产生进位或借位时，Ac＝1；否则，Ac＝0。
3）F0（PSW.5）用户设定标志位由用户使用的一个状态标志位，可用指令来使它置1或清0，控制程序的流
向。用户应充分利用。 4）RS1、RS0（PSW.4、PSW.3）4
组工作寄存器区选择
选择片内RAM区中的4组工作寄存器区中的某一组为当前工作寄存区见表2-2。
5）OV（PSW.2）溢出标志位
当执行算术指令时，用来指示运算结果是否产生溢出。如果结果产生溢出，OV=1；否则，OV=0。
6）PSW.1位
保留位
7）P（PSW.0）奇偶标志位
指令执行完，累加器A中“1”的个数是奇数还是偶数。
P=1，表示A中“1”的个数为奇数。
P=0，表示A中“1”的个数为偶数。
此标志位对串行通信有重要的意义，常用奇偶检验的方法来检验数据串行传输的可靠性。
表2-2 RS1 RS0与四组寄存器区的对应关系
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